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9 GHz DIVIDE-BY-4 DYNAMIC PRESCALER
FEATURES * * *
WIDE OPERATING FREQUENCY RANGE: fIN = 3.5 to 9.0 GHz (TA = 25C) DIVISION RATIO OF 4 GUARANTEED OPERATING TEMPERATURE RANGE: -25C to +75C
Input Power, PIN (dBm)
+10
UPG503B
INPUT POWER vs. INPUT FREQUENCY
VDD = 3.8V VSS1 = 0V VSS2 = - 2.2 V (VGG1,2 OPEN) TA = -25C to +75C
Recommended Operating Region
0
DESCRIPTION
The UPG503B is a GaAs divide-by-4 prescaler that is capable of operating up to 9 GHz. It is designed to be used in the frequency synthesizers of microwave communication systems and measurement equipment. The UPG503B is a dynamic divider. It employs buffered FET logic (BFL). The UPG503B is available in a hermetic 8-lead ceramic flat package.
-10
TA = -25C TA = +25C TA = +75C 0 1 2 3 4 5 6 7 8 9 10
Input Frequency, f (GHz)
ELECTRICAL CHARACTERISTICS1
(TA = 25C, VDD = 3.8 V, VSS1 = 0 V, VSS2 = -2.2 V) UPG503B BF08 UNITS mA mA mA GHz GHz dBm dBm dBm dBm C/W 9.0 3.0 0 0 21 8.6 MIN 40 TYP 80 27 53 9.0 3.5 3.7 10.0 10.0 3 3 10 93 MAX 130
PART NUMBER PACKAGE OUTLINE SYMBOLS IDD ISS1 ISS2 fIN(U) fIN(L) PIN POUT RTH PARAMETERS AND CONDITIONS Supply Current Sink Current2 ISS1 = IDD - ISS2
Sink Current2 Upper Limit of Input Frequency, PIN = +9 to +10 dBm Lower Limit of Input Frequency, PIN = +9 to +10 dBm Input Power, fIN = 3.7 to 8.6 GHz fIN = 5.0 to 7.4 GHz Output Power, fIN = 8.6 GHz, PIN = +10 dBm fIN = 3.7 GHz, PIN = +10 dBm Thermal Resistance, Channel to Case
Note: 1.Device may exhibit low frequency spur typically below 150 Hz and -45 dBm. 2. Current is positive into the IDD pin and returns through the ISS1 and ISS2 pins.
California Eastern Laboratories
UPG503B ELECTRICAL CHARACTERISTICS
TA = 25C to +75C, VDD = 3.8 V, VSS1 = 0 V, VSS2 = -2.2 V) UPG503B BF08 UNITS mA mA mA GHz GHz dBm dBm dBm dBm 9.0 4.0 -1.0 -1.0 8.0 4.0 10.0 10.0 2.0 2.0 MIN TYP 80 27 53 MAX
PART NUMBER PACKAGE OUTLINE SYMBOLS IDD ISS1 ISS2 fIN(U) fIN(L) PIN POUT PARAMETERS AND CONDITIONS Supply Current Sink Current1 ISS1 = IDD - ISS2 Sink Current1 Upper Limit of Input Frequency, PIN = +9 to +10 dBm Lower Limit of Input Frequency, PIN = +9 to +10 dBm Input Power, fIN = 4.0 to 8.0 GHz fIN = 5.0 to 7.0 GHz Output Power fIN = 8.0 GHz, PIN = +10 dBm fIN = 4.0 GHz, PIN = +10 dBm
Note: 1. Current is positive into the IDD pin and returns through the ISS1 and ISS2 pins.
ABSOLUTE MAXIMUM RATINGS1
SYMBOLS VDD-VSS1 VSS2-VSS1 PIN PT TSTG TC PARAMETERS Supply Voltage Supply Voltage Input Power Total Power Dissipation2 Storage Temperature Case Temperature UNITS V V dBm W C C
(TA = 25C)
2.5
POWER DERATING CURVE
RATINGS 5.0 -5.0 13 1.5 -65 to +175 -65 to +125 Total Power Dissipation, PT (W)
2.0
1.5
1.0
TCASE MAX = 125C
0.5
Notes: 1. Operation in excess of any one of these conditions may result in permanent damage. 2. TC 125C
0 0 50 100 110 150 200 250
Case Temperature, TC (C)
TYPICAL PERFORMANCE CURVES (TA = 25)
SSB PHASE NOISE VS. OFFSET FROM CARRIER fIN = 6.82 GHz, TA = 25C
-60 -70
OUTPUT POWER vs. INPUT FREQUENCY
SSB Phase Noise (dBc/Hz)
Output Power, POUT (dBm)
-80 -90 -100 -110 -120 -130 -140 -150 -160 10 100 1K 10K 100K 1M
+10
0
-10
VDD = 3.8V VSS1=0V VSS2=-2.2V (VGG1,2 OPEN) TA = -25C TA = +25C TA = +75C
0 1 2 3 4 5 6 7 8 9 10
Offset from Carrier (Hz)
Input Frequency, fIN (GHz)
POWER SUPPLY CONFIGURATIONS (VGG1 and VGG2 are normally open)
CONFIGURATION 1 2 Bias Supply
Zo = 50 C 5 IN See Note 1 6 VGG1 OPEN 7 VGG2 OPEN VSS2 (-2.2 V) 8 VSS2 10 F C OUT 1 C Zo = 50 OUT VSS1 2 NC 3 OPEN VSS1 (0 V) GND VDD 4 C 10 F
IN
VDD (3.8 V)
VDD = 3.8 V VSS1 = 0 V (GND) VSS2 = -2.2 V C: 1000 - 5000 pF Chip Capacitor
CONFIGURATION 2 Single Positive Bias Supply
Zo = 50 IN See Note 1 6 VGG1 OPEN 7 VGG2 OPEN GND (0 V) VSS2 8 VSS2 OUT 1 C VSS1 2 NC 3 OPEN C 2.2 V OUT Zo = 50 C 5 IN VDD 4 C 10 F 10 F *
VDD (+6 V)
VDD = +6.0 V VSS2 = 0 V (GND) C: 1000 - 5000 pF Chip Capacitor
* VSS1 should be connected to GND through a 2.2 V Zener Diode
(RD2.2FB or IN3394).
CONFIGURATION 3 Single Negative Bias Supply
Zo = 50 IN See Note 1 6 VGG1 OPEN 7 VGG2 OPEN VSS2 (-6 V) 8 VSS2 10 F C OUT 1 C VSS1 2 C 2.2 V OUT Zo = 50 NC 3 OPEN -6 V* 10 F C 5 IN VDD 4
VDD = 0 V (GND) VSS2 = -6 V C: 1000 - 5000 pF Chip Capacitor
* For VSS1, the bias voltage of -6.0 should be applied through a 2.2 V
Zener Diode (RD2.2FB or IN3394).
Notes: 1. Because of the high internal gain and gain compression of the UPG503B, the device is prone to self-oscillation in the absence of an RF input signal. This self-oscillation can be suppressed by either of the following means: * Add a shunt resistor to the RF input line. Typically a resistor value between 50 and 1000 ohms will suppress the selfoscillation (see the test circuit schematic). * Apply a negative voltage through a 1000 ohm resistor to the normally open VGG1 connection. Typically voltages between 0 and -9 volts will suppress the self-oscillation. Both of these approaches will reduce the input sensitivity of the device (by as much as 3 dB for a 50 ohm shunt resistor), but otherwise have no effect on the reliability or electrical characteristics of the device.
UPG503B OUTLINE DIMENSIONS (Units in mm)
UPG503B PACKAGE OUTLINE BF08
7.00.5 1.27 1.27 1.27 0.1 0.1 0.1
1.7 MAX
8
7
6
5
10.40.5 2.6 4.40.2
1
2 0.4 5.00.2
3
4 +0.05 0.2 -0.02
LEAD CONNECTIONS: 1. 2. 3. 4. OUTPUT VSS1 NC* VDD 5. 6. 7. 8. INPUT VGG1 VGG2 VSS2
* No Connection
EXCLUSIVE NORTH AMERICAN AGENT FOR
RF, MICROWAVE & OPTOELECTRONIC SEMICONDUCTORS
CALIFORNIA EASTERN LABORATORIES * Headquarters * 4590 Patrick Henry Drive * Santa Clara, CA 95054-1817 * (408) 988-3500 * Telex 34-6393 * FAX (408) 988-0279 24-Hour Fax-On-Demand: 800-390-3232 (U.S. and Canada only) * Internet: http://WWW.CEL.COM PRINTED IN USA ON RECYCLED PAPER -4/97 DATA SUBJECT TO CHANGE WITHOUT NOTICE

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